elsif z>=40 then d(7 downto 4):="0100"; z:=z-40;
elsif z>=30 then d(7 downto 4):="0011"; z:=z-30;
elsif z>=20 then d(7 downto 4):="0010"; z:=z-20;
elsif z>=10 then d(7 downto 4):="0001"; z:=z-10;
else d(7 downto 4):="0000";
end if;
if z>=9 then d(3 downto 0):="1001";
elsif z>=8 then d(3 downto 0):="1000";
elsif z>=7 then d(3 downto 0):="0111";
elsif z>=6 then d(3 downto 0):="0110";
elsif z>=5 then d(3 downto 0):="0101";
elsif z>=4 then d(3 downto 0):="0100";
elsif z>=3 then d(3 downto 0):="0011";
elsif z>=2 then d(3 downto 0):="0010";
elsif z>=1 then d(3 downto 0):="0001";
else d(3 downto 0):="0000";
end if;
y<=d;
end process;
end one;
显示模块程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xian is
port(ain: in std_logic_vector(19 downto 0);
clk3:in std_logic;
chs:out std_logic_vector(2 downto 0);
result:out std_logic_vector(7 downto 0)
);
end xian;
architecture aa of xian is
signal resultz,resulto,resultt,resulte,resultf,resultv: std_logic_vector(7 downto 0);
signal sel,seo,set,see,sef:std_logic_vector(3 downto 0);
signal ch:std_logic_vector(2 downto 0);
begin
sel<=ain(3 downto 0);
seo<=ain(7 downto 4);
set<=ain(11 downto 8);
see<=ain(15 downto 12);
sef<=ain(19 downto 16);
process(sel,seo,set,see,sef)
begin
if sel="0000" then resultz<="00111111";
elsif sel="0001" then resultz<="00000110";
elsif sel="0010" then resultz<="01011011";
elsif sel="0011" then resultz<="01001111";
elsif sel="0100" then resultz<="01100110";
elsif sel="0101" then resultz<="01101101";
elsif sel="0110" then resultz<="01111101";
elsif sel="0111" then resultz<="00000111";
elsif sel="1000" then resultz<="01111111";
elsif sel="1001" then resultz<="01101111";
else resultz<="00000000";
end if;
if seo="0000" then resulto<="00111111";
elsif seo="0001" then resulto<="00000110";
elsif seo="0010" then resulto<="01011011";
elsif seo="0011" then resulto<="01001111";
elsif seo="0100" then resulto<="01100110";
elsif seo="0101" then resulto<="01101101";
elsif seo="0110" then resulto<="01111101";
elsif seo="0111" then resulto<="00000111";
elsif seo="1000" then resulto<="01111111";
elsif seo="1001" then resulto<="01101111";
else resulto<="00000000";
end if;
if set="0000" then resultt<="00111111";
elsif set="0001" then resultt<="00000110";
elsif set="0010" then resultt<="01011011";
elsif set="0011" then resultt<="01001111";
elsif set="0100" then resultt<="01100110";
elsif set="0101" then resultt<="01101101";
elsif set="0110" then resultt<="01111101";
elsif set="0111" then resultt<="00000111";
elsif set="1000" then resultt<="01111111";
elsif set="1001" then resultt<="01101111";
else resultt<="00000000";
end if;
if see="0000" then resulte<="00111111";
elsif see="0001" then resulte<="00000110";
elsif see="0010" then resulte<="01011011";
elsif see="0011" then resulte<="01001111";
elsif see="0100" then resulte<="01100110";
elsif see="0101" then resulte<="01101101";
elsif see="0110" then resulte<="01111101";
elsif see="0111" then resulte<="00000111";
elsif see="1000" then resulte<="01111111";
elsif see="1001" then resulte<="01101111";
else resulte<="00000000";
end if;
if sef="0000" then resultf<="00111111";
elsif sef="0001" then resultf<="00000110";
elsif sef="0010" then resultf<="01011011";
elsif sef="0011" then resultf<="01001111";
elsif sef="0100" then resultf<="01100110";
elsif sef="0101" then resultf<="01101101";
elsif sef="0110" then resultf<="01111101";
elsif sef="0111" then resultf<="00000111";
elsif sef="1000" then resultf<="01111111";
elsif sef="1001" then resultf<="01101111";
else resultf<="00000000";
end if;
end process;
process(clk3)
begin
ch<=ch+1;
chs<=ch+1;
end if;
if ch<="000" then
result<=resultz;
elsif ch<="001" then
result<=resulto;
elsif ch<="010" then
result<=resultt;
elsif ch<="011" then
result<=resultf;
elsif ch<="101" then
result<="00000000";
elsif ch<="110" then
result<="00000000";
elsif ch<="111" then
result<="00000000";
end if;
end process;
end aa;
截取模块程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;
entity jiequ is
port(shuru:in std_logic_vector(15 downto 0);
);
end jiequ;
architecture jie of jiequ is
begin
shuchu<=shuru(15 downto 8);
end jie;
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