图4.-3-7 蓄电池自动充电电路
4.4 VHDL源程序
键盘输入去抖电路的VHDL源程序
DCFQ.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DCFQ IS
PORT(CLK,CLRN,PRN,D:IN STD_LOGIC);
Q:OUT STD_LOGIC);
END ENTITY DCFQ;
ARCHITECTURE ART OF DCFQ IS
BEGIN
PROCESS (CLK,CLRN,PRN)
BEGIN
IF CLRN=’0’AND PRN=’1’THEN
Q<=’0’;
ELSIF CLRN=’1’AND PRN=’0’THEN
Q<=’1’;
ELSIF CLK’EVENT AND CLK=’1’THEN
Q<=D;
END IF;
END PROCESS;
END ARCHITECTURE ART;
--DEBOUNCING.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY ALTERA;
USE ALTER.MAXPLUS2.ALL;
ENTITY DEBOUCING IS
PORT(D_IN,CLK:IN STD_LOGIC;
DD1,DD0,QQ1,QQ0:OUT_LOGIC;
D_OUT,D_OUT1:OUT STD_LOGIC);
END ENTITY DEBOUNCING;
ARCHITECTURE ART OF DEBOUNCING IS
COMPONENT DCFQ IS
PORT(CLK,CLRN,PRN,D:IN STD_LOGIC;
Q:OUT STD_LOGIC);
END COMPONENT DCFQ;
SIGNAL VCC,INV_D:STD_LOGIC;
SIGNAL Q0,Q1:STD_LOGIC;
SIGNAL D1,D0:STD_LOGIC;BEGIN
VCC<=’1’;
INV_D<=NOT D_IN;
U1CFQ PORT MAP(CLK=>CLK,CLRN=>INV_D,PRN=>VCC,D=>VCC,Q=>Q0);
U2CFQ PORT MAP(CLK=>CLK,CLRN=>Q0,PRN=>VCC,D=>VCC,D=>VCC,Q=>Q1);
PROCESS (CLK)
BEGIN
IF CLK’EVENT AND CLK=’1’THEN
D0<=NOT Q1;
D1<=D0;
END IF;
END PROCESS;
DD0<=D0;DD1<=D1;QQ1<=Q1;QQ0<=Q0;
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--KEYBOARD.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSINGNED.ALL;
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