clr<='1' ;
when 0=>en<='1';
load<='0';
clr<='0';
end case;
end if;
end process;
end Behavioral;
十进制计数器:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count10 is
Port ( reset : in std_logic;
enable : in std_logic;
clk : in std_logic;
cout : out std_logic;
q : out std_logic_vector(3 downto 0));
end count10;
architecture Behavioral of count10 is
signal q_tmp: std_logic_vector(3 downto 0);
begin
process(clk)
begin
if (clk 'event and clk='1')then
if reset='1' then
q_tmp<="0000";
elsif enable='1' then
if q_tmp="1001" then
q_tmp<="0000";
else q_tmp<=q_tmp+1;
end if;
end if;
end if;
q<=q_tmp;
if (q_tmp="1001" and enable='1') then cout<='1';
else cout<='0';
end if;
end process;
end Behavioral;
锁存器
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity latch is
Port ( data : in std_logic_vector(23 downto 0);
oe: in std_logic;
g : in std_logic;
q : out std_logic_vector(23 downto 0));
end latch;
architecture Behavioral of latch is
signal q_tmp: std_logic_vector (23 downto 0);
begin
process (oe,g)
begin
if oe='0' then
if g'event and g='1' then
q_tmp<=data;
end if;
else q<=q_tmp;
end if;
end process;
end Behavioral;
扫描电路:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity scan is
Port ( clk0: in std_logic;
vin : in std_logic_vector(23 downto 0);
vout : out std_logic_vector(3 downto 0);
d : out std_logic_vector(2 downto 0));
end scan;
architecture Behavioral of scan is
signal c: integer range 0 to 5;
begin
process(clk0)
begin if (clk0 'event and clk0='1') then
if c=5 then c<=0;
else c<=c+1;
end if;
case c is when 0=>vout<=vin(3)&vin(2)&vin(1)&vin(0);
d<="101";
when 1=>vout<=vin(7)&vin(6)&vin(5)&vin(4);
d<="100";
when 2=>vout<=vin(11)&vin(10)&vin(9)&vin(8);