d<="011";
when 3=>vout<=vin(15)&vin(14)&vin(13)&vin(12);
d<="010";
when 4=>vout<=vin(19)&vin(18)&vin(17)&vin(16);
d<="001";
when 5=>vout<=vin(23)&vin(22)&vin(21)&vin(20);
d<="000";
end case;
end if;
end process;
end Behavioral;
译码电路:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decode is
Port ( din : in std_logic_vector(3 downto 0);
dout : out std_logic_vector(6 downto 0));
end decode;
architecture Behavioral of decode is
begin
process(din)
begin
case din is when"0000"=>dout<="0111111";
when"0001"=>dout<="0000110";
when"0010"=>dout<="1011011";
when"0011"=>dout<="1001111";
when"0100"=>dout<="1100110";
when"0101"=>dout<="1101101";
when"0110"=>dout<="1111101";
when"0111"=>dout<="1011000";
when"1000"=>dout<="1111111";
when"1001"=>dout<="1101111";
when others=>dout<="0000000";
end case;
end process;
end Behavioral;
实验总结:
1:控制电路的EN,CLR输出要接缓冲器,否则不能驱动译码电路.
2:扫描分频器的输出频率要在200----1000HZ之间.
3:锁存器的G输入端应是跳变沿触发,否则频率不能锁定.
4:如果要测多个频率,可设计不同的分频器,并用多选一电路实现.
5辣个十进制计数器在原理图上直接级联,如果在VHDL层面用PORTMAP语句实现,可以使原理图更简洁.