语音信号μ/A律压缩的DSP软件实现(英文文献+中期报告)
vectors are soft — meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch instruction: either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate interrupt service routine with minimal overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page.
NOTE: The hardware reset (RS) vector cannot be remapped, because the hardware reset loads the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program space. In addition, for the ’54x, 128 words are reserved in the on-chip ROM for device-testing purposes. Application code written to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h–FF7Fh in program space.
1.4.7.2 Extended Program Memory
Selected ’54x devices use a page-extended memory scheme in program space to allow access of up to 8M of program memory. This extended program memory is organized into a maximum of 128 pages (0–127), each 64K in length. Devices which implement the extended program memory scheme include the following additional features:
Maximum of seven additional address lines (for a total of 23). An extra memory-mapped register [program counter extension register (XPC)]. Six new instructions for addressing extended program memory space:
FB[D] — Far branch
FBACC[D] — Far branch to the location specified by the value in accumulator A or accumulator B
FCALA[D] — Far call to the location specified by the value in accumulator A or accumulator B
FCALL[D] — Far call
FRET[D] — Far return
FRETE[D] — Far return with interrupts enabled
Two ’54x instructions are extended
READA — Read program memory addressed by accumulator A and store in data memory
WRITA — Write data to program memory addressed by accumulator A for more information on these six new instructions and the two extended instructions, refer to the instruction set summary (Table 1–11) and to the TMS320C54x DSP Reference Set, Volume 2, Mnemonic Instruction Set, literature number SPRU172. And for more information on extended program memory, refer to the TMS320C54x DSP Reference Set, Volume 1, CPU and Peripherals, literature number SPRU131.
Table 1–5 shows the extended program addressing options available in the ’54x family
Table 1–5. Extended Program Memory Addressing Options
1.4.8 Data Memory
The data memory space on the ’54x device addresses 64K of 16-bit words.
The device automatically accesses the on-chip RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device automatically generates an external access.
The advantages of operating from on-chip memory are as follows:
Higher performance because no wait states are required
Higher performance because of better flow within the pipeline of the CALU
Lower cost than external memory
Lower power than external memory
In addition to general-purpose data memory, the CPU maintains a set of memory-mapped registers in data memory for processor configuration and configuration/communication with the device peripherals. For detailed information on the implementation of the memory-mapped CPU and peripheral control registers, see the device-specific data sheets.
1.5 On-Chip Peripherals
All the ’54x devices have the same CPU structure; however, they have different on-chip peripherals connected to their CPUs. The on-chip peripheral options provided are:
Software-programmable wait-state generator
Programmable bank-switching
Parallel I /O ports
DMA controller
Host-port interface (standard 8-bit, enhanced 8-bit, and 16-bit)
Serial ports (standard, TDM, BSP, and McBSP)
General-purpose I/O pins
16-bit timer with 4-bit prescaler
Phase-locked loop (PLL) clock generator
1.5.1 Software-Programmable Wait-State Generators
The software-programmable wait-state generator can be used to extend external bus cycles to interface with slower off-chip memory and I/O devices. The software wait-state generator is incorporated without any external hardware. For off-chip memory access, a number of wait states can be specified for every 32K-word block of program and data memory space, and for one 64K-word block of I/O space within the software wait-state register (SWWSR). The software wait-state generator is programmable up to 7 or 14 wait states depending on the device. For more specific information on the software wait-state generation capability, see the device-specific data sheet.
1.5.2 Programmable Bank-Switching
Programmable bank-switching can be used to insert one cycle automatically when crossing memory-bank boundaries inside program memory or data memory space. One cycle can also be inserted when crossing from program-memory space to data-memory space (’54x) or from one program memory page to another program memory page on selected devices. This extra cycle allows memory devices to release the bus before other devices start driving the bus; thereby avoiding bus contention. The size of memory bank for the bank-switching is defined by the bank-switching control register (BSCR). For specific information on the bank-switching capabilities of a specific device, see the device-specific data sheet.
1.5.3 Parallel I/O Ports
Each ’54x device has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The devices can interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.
1.5.6 Serial Ports
The ’54x devices provide high-speed, full-duplex serial ports that allow direct interface to other ’54x devices, codecs, and other devices in a system. There is a standard serial port, a time-division-multiplexed (TDM) serial port, a buffered serial port (BSP), and a multichannel buffered serial port (McBSP).
Table 1–1 shows the availability of each of the serial port types in the ’54x family.
1.5.6.1 Standard Serial Port
The general-purpose serial port utilizes two memory-mapped registers for data transfer: the data-transmit register (DXR) and the data-receive register (DRR). Both of these registers can be accessed in the same manner as any other memory location. The transmit and receive sections of the serial port each have associated clocks,
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