语音信号μ/A律压缩的DSP软件实现(英文文献+中期报告)
frame-synchronization pulses, and serial-shift registers; and serial data can be transferred either in bytes or in 16-bit words.
Serial port receive and transmit operations can generate their own maskable transmit and receive interrupts (XINT and RINT), allowing serial-port transfers to be managed through software. The ’54x serial ports are double-buffered and fully static.
1.5.6.2 TDM Serial Port
The TDM port allows the device to communicate through time-division multiplexing with up to seven other ’54x devices with TDM ports. Time-division multiplexing is the division of time intervals into a number of subintervals with each subinterval representing a prespecified communications channel. The TDM port serially transmits 16-bit words on a single data line (TDAT) and destination addresses on a single address line (TADD). Each device can transmit data on a single channel and receive data from one or more of the eight channels, providing a simple and efficient interface for multiprocessing applications. A frame synchronization pulse occurs once every 128 clock cycles, corresponding to the transmission of one 16-bit word on each of the eight channels. Like the general-purpose serial port, the TDM port is double-buffered on both input and output data.
1.5.6.3 Buffered Serial Port (BSP)
The buffered serial port (BSP) consists of a full-duplex, double-buffered serial-port interface and an autobuffering unit (ABU). The serial port block of the BSP is an enhanced version of the standard serial port. The ABU allows the serial port to read/write directly to the ’54x internal memory using a dedicated bus independent of the CPU. This results in minimal overhead for serial port transactions and faster data rates.
When autobuffering capability is disabled (standard mode), serial port transfers are performed under software control through interrupts. In this mode, the ABU is transparent and the word-based interrupts (WXINT and WRINT) provided by the serial port are sent to the CPU as transmit interrupt (XINT) and receive interrupt (RINT). When autobuffering is enabled, word transfers are done directly between the serial port and the ’54x internal memory using ABU-embedded address generators.
The ABU has its own set of circular-addressing registers with corresponding address-generation units. Memory for the buffers resides in 2K words of the ’54x internal memory. The length and starting addresses of the buffers are user-programmable. A buffer-empty/buffer-full interrupt can be posted to the CPU. Buffering is easily halted by an autodisabling capability. Autobuffering capability can be enabled separately for transmit and receive sections. When autobuffering is disabled, operation is similar to that of the general-purpose serial port.
The BSP allows transfer of 8-, 10-, 12-, or 16-bit data packets. In burst mode, data packets are directed by a frame synchronization pulse for every packet. In continuous mode, the frame synchronization pulse occurs when the data transmission is initiated and no further pulses occur. The frame and clock strobes are frequency- and polarity-programmable. The BSP is fully static and operates at arbitrarily low clock frequencies. The BSP maximum operating frequency for ’54x devices up to 50 MIPS is CLKOUT. For higher-speed ’54x devices, the BSP maximum operating frequency is 50 Mbps at 20 ns.
Buffer Misalignment (BMINT) Interrupt (’549 only)
The BMINT interrupt is generated when a frame sync occurs and the ABU transmit or receive buffer pointer is not at the top of the buffer address. This is useful for detecting several potential error conditions on the serial interface, including extraneous and missed clocks, and frame sync pulses. A BMINT interrupt, therefore, indicates that one or more words may have been lost on the serial interface.
BMINT is useful for detecting buffer misalignment only when the buffer pointer(s) are initially loaded with the top-of-buffer address, and a frame of data contains the same number of words as the buffer length. These are the only conditions under which a frame sync occurring at a buffer address, other than the top of buffer, constitute an error condition. In cases where these conditions are met, a frame sync always occurs when the buffer pointer is at the top of buffer address, if the interface is functioning properly.
If BMINT is enabled under conditions other than those stated above, interrupts may be generated under circumstances other than actual buffer misalignment. In these cases, BMINT should generally be masked in the IMR register so that the processor will ignore this interrupt.
BMINT is available when operating autobuffering mode with continuous transfers, the FIG bit cleared to 0, and external serial clocks or frames. The BSP0 and BSP1 BMINT bits in the IMR and IFR registers are bits 12 and 13, respectively (bit 15 is the MSB). The interrupt vector locations of IMR and IFR are 070h and 074h, respectively.
1.5.6.4 Multichannel Buffered Serial Port (McBSP)
The ’54x devices provide high-speed, full-duplex, multichannel buffered serial ports that allow direct interface to other ’54x devices, codecs, and other devices in a system. The multichannel buffered serial ports (McBSPs) are based on the standard serial port interface found on other ’54x devices. Like its predecessors, the McBSP provides:
Full-duplex communication
Double-buffer data registers which allow a continuous data stream
Independent framing and clocking for receive and transmit In addition, the McBSP has the following capabilities:
Direct interface to:
T1/E1 framers
MVIP switching-compatible and ST-BUS compliant devices
IOM-2 compliant devices
AC97-compliant devices
IIS-compliant devices
Serial peripheral interface
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits
m-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
The McBSPs consist of separate transmit and receive channels that operate completely independently. The external interface of each McBSP consists of the following pins:
BCLKX Transmit reference clock
BDX Transmit data
BFSX Transmit frame sync
BCLKR Receive reference clock
BDR Receive data
BFSR Receive frame sync
BCLKS External clock reference for the programmable clock generator.
The first six pins listed are identical to the previous serial port interfaces on the ’C5000 family of DSPs. The BCLKS pin is an additional signal to provide a clock reference to the McBSP programmable clock generator. As a compatibility option, BCLKS is not implemented on some packages. On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX pins, respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register (DXR). Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR).
This structure allows DXR to be loaded with the next word to be sent while the transmission of the current word is in progress. On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins, respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received on the BDR pin is，shifted into a receive shift register (RSR) and then buffered in the receive buffer register (RBR). If DRR is empty, the RBR contents are copied into DRR. If not, RBR holds the data until DRR is available. This structure allows storage of the two previous words while the reception of the current word is in progress.
To maintain pin compatibility with previous devices, not all 54x devices with McBSPs implement the BCLKS pin. For this reason, select 54x devices allow either the receive clock pin (BCLKR) or the transmit clock pin (BCLKX) to be configured as the input clock to the sample rate generator. This enhancement is enabled through two register bits: pin control register (PCR) bit 7 – enhanced sample clock mode (SCLKME), and sample rate generator register 2 (SRGR2) bit 13 – McBSP sample rate generator clock mode (CLKSM).
SCLKME is an addition to the PCR contained in the McBSPs on previous ’C5000 devices. The selection of the sample rate generator (SRG) clock input source is made by the combination of the CLKSM and SCLKME bit values.
Table 1–9. External Clock Source For Sample Rate Generator Supported
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