语音信号μ/A律压缩的DSP软件实现(英文文献+中期报告)
When either of the bidirectional pins, BCLKR or BCLKX, is configured as the clock input, its output buffer is automatically disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured as the SRG input.
In this case, both the transmitter and receiver circuits can be synchronized to the SRG output by setting the PCR bits (9:8) for CLKXM = 1 and CLKRM = 1. However, the SRG output is only driven onto the BCLKX pin because the BCLKR output is automatically disabled.
The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP interrupts, event signals, and status flags. The DMA is capable of handling data movement between the McBSPs and memory with no intervention from the CPU.
In addition to the standard serial port functions, the McBSP provides programmable clock and frame sync generation. Among the programmable functions are:
Frame sync pulse width
Frame period
Frame sync delay
Clock reference (internal vs. external)
Clock division
Clock and frame sync polarity
The on-chip companding hardware allows compression and expansion of data in either m-law or A-law format. When companding is used, transmit data is encoded according to the specified companding law and received data is decoded to 2s complement format.
The McBSP allows multiple channels to be independently selected for the transmitter and receiver. When the multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using TDM data streams, the DSP CPU can be programmed to process as many data streams as necessary for the specific application. Thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for transmission and reception. Up to a maximum of 32 channels in a 128-channel bit stream can be enabled or disabled. Select devices have been enhanced to allow the enabling or disabling of up to 128 channels in a 128-channel bit stream. Devices supporting this enhancement are listed in Table 1–10.
Table 1–10. Devices Supporting Up To 128 Channels of TDM
The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface protocol. Clock-stop mode works with only single-phase frames and one word per frame. The word sizes supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation.
When the McBSP is configured to operate in serial peripheral interface mode, both the transmitter and the receiver operate together as a master or as a slave.
The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU clock frequency divided by 2.
1.5.7 General-Purpose I/O (GPIO) Pins
The ’54x family of devices provide general-purpose I/O pins that can be read or written through software control. All devices support two GPIO pins.
BIO – A general input upon which conditional instructions can be based.
XF – An external flag output that can be driven low or high under software control.
BIO and XF are often used for handshaking functions. In addition to the above described pins, other GPIO pins are available on selected devices. Some GPIO pins are multiplexed with the McBSP/HPI pin functions and some GPIO pins are dedicated. The multiplexed pins can be used for a GPIO function or a McBSP/HPI function under software control. However, the dedicated GPIO pins are always used for general-purpose I/O. See Table 1-1 for the availability of GPIO pins on each device.
1.5.8 Hardware Timer
The ’54x devices feature a 16-bit timing circuit with a four-bit prescaler. The timer counter is decremented by one at every CLKOUT cycle. Each time the counter decrements to zero, a timer interrupt is generated. The timer can be stopped, restarted, reset, or disabled by specific status bits.
1.5.9 Clock Generator
There are two basic options for clock generation on the ’54x family of devices: divide-by-two and PLL. In the first option, the CPU clock is generated by dividing the input clock provided as X2/CLKIN by two. The second option uses a phase-locked loop circuit to generate a CPU clock that is a multiple of the frequency of the input clock. The PLL method allows a high-frequency internal CPU clock to be generated from a low-frequency external clock. Maintaining a low-frequency clock off chip reduces system power consumption, reduces clock-generated electromagnetic interference (EMI), and facilitates the use of less expensive external crystals or oscillators. The desired clock options are initially selected with the clock mode (CLKMD) pins.
The clock options available on the ’54x family vary depending on device. However, all ’54x devices provide the divide-by-two clock capability. On devices that provide a hardware PLL, the desired multiplication factor is chosen by the state of the clock mode pins only.
1.5.9.1 Hardware PLL
There are two types of hardware PLL providing different sets of multiplication factors. The option-one hardware PLL provides divide-by-two operation and multiplication factors of 1, 1.5, 2, or 3. The option-two hardware PLL provides divide-by-two operation and multiplication factors of 1, 4, 4.5, or 5.
1.5.9.2 Software PLL
The software PLL is programmable and the clock multiplication factor can be changed under software control. The initial clock mode setting is determined by the state of the clock mode pins and then the PLL can be programmed to change the clock mode. The software PLL provides multiplication factors ranging from 0.25 to 16. The software PLL also provides a built-in programmable lock-delay counter that prevents the PLL from clocking the CPU until a predefined lock-up time has elapsed, thereby ensuring that the PLL has had enough time to lock onto the input clock.
The input clock to the DSP is provided at the X2/CLKIN pin and can be produced by an external clock source (i.e., an integrated circuit oscillator), or can be produced by the on-chip oscillator on the DSP with as little as three external components: a crystal or ceramic resonator, and two resistors. The PLL options available on each of the ’54x family DSPs are included in the peripherals section of Table 1–1. For more detailed information on the operation of the clock options and the hardware or software PLL, consult the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131).
Copyright W 2001, Texas Instruments Incorporated
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