DDS函数信号发生器的设计与实现 第3页

DDS函数信号发生器的设计与实现 第3页
程序：加法器：ADDER32B
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER32B IS
 PORT( A1: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    B1: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    S1: OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
 END ADDER32B;
ARCHITECTURE BEHAV OF ADDER32B IS
 BEGIN
 S1 <= A1+B1;
 END BEHAV;
寄存器:  REG32BIT
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY reg32bit IS
    PORT (  CLK: IN STD_LOGIC;
           DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
           DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
END reg32bit;
ARCHITECTURE one OF reg32bit IS
BEGIN
PROCESS(CLK,DIN)
   BEGIN
   IF CLK'EVENT AND CLK = '1' THEN    -- 时钟到来时，锁存输入数据
            DOUT <= DIN;
        END IF;
    END PROCESS;
END;
数据选择器
library ieee;
use ieee.std_logic_1164.all;
entity selec3_1 is
port(a,b : in std_logic;
 cin1,cin2,cin3 : in std_logic_vector(7 downto 0);
 cout : out std_logic_vector(7 downto 0)
 );
end;
architecture arc of selec3_1 is
signal ab : std_logic_vector(1 downto 0);
begin
ab <= a&b;
process(ab,cin1,cin2,cin3)
begin
case ab is
when "00" => cout <= cin1;
when "01" => cout <= cin2;
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end process;
end;
译码处理
按键处理部分
Library IEEE;
Use IEEE.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;
Entity key_show is
Port(                                  clk_s: in std_logic;
                                mode,add,sub: in std_logic;
                                 q2,q3,q4: out std_logic_vector(23 downto 0);
                                          q1: out std_logic_vector(13 downto 0);
                                      LED7S: out std_logic_vector(6 downto 0);
                                     SEL_OUT: out std_logic_vector(2 downto 0);
         da_1_out,da_2_out,da_3_out,da_4_out: out std_logic_vector(3 downto 0));
end key_show;
architecture arch of key_show is
  signal     Q  : std_logic_vector(24 downto 0);
  signal    mode_out_bak,SEL  : std_logic_vector(2 downto 0);
  signal    da_4,da_3,da_2,da_1,da_4B,da_3B,da_2B,da_1B,A:  std_logic_vector(3 downto 0);
  signal    da_4_sel,da_3_sel,da_2_sel,da_1_sel,clk,clk2:  std_logic;
begin
q1<="10000110001101";
q2<="000000010100111110001011";
q3<="000011010001101101101110";
q4<="100000110001001001001100";

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