if (reset='0') then
count <= "0000000";
elsif (sethour='0') then
enhour <= clk1;
elsif (clk' event and clk='1') then
if (count(3 downto 0)="1001") then
if (count <16#60#) then
if (count="1011001") then
enhour<='1';
count<="0000000";
ELSE
count<=count+7;
end if;
else
count<="0000000";
end if;
elsif(count <16#60#) then
count <= count + 1;
enhour<='0' after 100 ns;
else
count<="0000000";
end if;
end if;
end process;
END fun;
分计时器也是一个60进制的计数器，它从秒计时器的脉冲输出端接受脉冲信号。每当一个脉冲信号来时，分就自动加1，当分计满60时，发出一个脉冲信号给时组件，再将本身清零。这样，每计满60MIN，小时就加1，正好按着正常的时间规律计时。该模块还能对分进行数字调整，并可以将其全部清零。
3.3.3时计时器（VHDL语言）
代码如下：
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY hour IS
PORT(
clk,reset: IN STD_LOGIC;
daout: out std_logic_vector (5 downto 0));
END entity hour;
ARCHITECTURE fun OF hour IS
SIGNAL count: STD_LOGIC_VECTOR( 5 downto 0);
BEGIN
daout <= count;
process ( clk,reset)
begin
if (reset='0') then
count <= "000000";
elsif (clk' event and clk='1') then
if (count(3 downto 0)="1001") then
if (count <16#24#) then
count<=count + 7;
else
count<="000000";
end if;
elsif(count <16#24#) then
count <= count + 1;
else
count<="000000";
end if;
end if;
end process;
END fun;原文请找腾讯752018766辣,文-论'文.网
http://www.751com.cn时计时器是一个24进制的计数器，它从分组件的脉冲信号输出端接受脉冲信号，每当一个脉冲信号来时，时就自动加1，并且输出个信号给时组件，直到计满24，再将本身清零。该组件还能对时进行数字调整，并可以将其全部清零。
3.3.4时间显示Deled（VHDL语言）
代码如下：
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY deled IS
PORT(num: IN std_logic_vector( 3 downto 0);
led: OUT std_logic_vector(6 downto 0));
END deled;
ARCHITECTURE fun OF deled IS
BEGIN
led <= "1111110" when num= "0000" else
"0110000" when num= "0001" else
"1101101" when num= "0010" else
"1111001" when num= "0011" else
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