求一篇有关CPLD的英文文献，要5000字左右，最好和基于CPLD的数字电压表设计有关。毕业设计要求翻译一篇5000字左右英文文献
Reliability Processing Of The Circuits In CPLD Design
Abstract: This paper studies on the elimination of the competitive and narrow pulse interference and on the reliability of the reset circuit in CPLD design . Methods of additional trigger ,delay superposition ,and larger loop feedback are introduced .The corresponding examples are discussed detailedly . The reliability problems of the circuits in CPLD design are solved effectively .
CPLD has been widely used in the design of electronic circuits and system because of its flexibility ,modifiability , and short development cycle . There inevitably exist unreliable factors in CPLD design such as competitive interference ,narrow pulse interference ,and false tigger [1 . This paper studies the reliability problems by examples and introduces corresponding process methods . The results are satisfied.
Ⅰ.Anti-interference Design of Complicated Circuits
A complicated pulse signal generator can be implemented in block diagram as shown in fig..1. Where ,all blocks can be integrated in CPLD except the waveform data storage , in which all turn time and corresponding state are stored. An EPROM can be used ,two bytes for each turn time and state . The active crystal oscillator is usually used for CPLD as the clock signal ,because its frequency is high, the divider is necessary to reduce the clock signal to an allowed frequency .Counter Ⅰis a timer unit in each period. Counter Ⅱ is a address pointer ,indicating the address to be accessed currently . The date latch records the turn of the output signal. The encoder produces the triggering signals of the data latch an the state latch.
The periodic control signal is reset of the divider and two counters, and is clock of additive counter to control high address of the EPROM if the output signal is different between periodic. Counter Ⅰ counts from 0 to each periodic . When its counted value equals the data in the data latch , the output of the comparer turns high level, and the output trigger is triggered, he output signal turns following the output of the state latch. At the same time, the NAND gate opens, the clock signal acts on the counter Ⅱand the encoder .At the rising edge, the counter Ⅱplus by Ⅰ,the data latch and state latch lock mew data, the next turn time and state from ERROM .The output of the comparer recovers low level. An output signal turn and data preset completed. Apparently ,as long as the time and the state for each turn is preset in the waveform data storage, the right signal output can be achieved.
However, the above-mentioned signals are out of order because of the existence of the competitive interference ,as shown in figure 2. Where ,the data latch is B=005(binary system of12-bit)and the state latch is ST=0 when counter Ⅰoutputs C=002. It means that INST, the output signal ,is to turn to low level at the time when C=005 But the simulation shows that INST turns in advance ,i.e, the output signal is error . The reason is competitive interference ,which appears on CMP, the output of the comparer ,when counter Ⅰchanges from 003 to 004 .Meanwhile, because of the competitive interference ,the NAND gate opens in advance and A, value of Counter Ⅱ, plusses by 1 , The time sequences of WR0 and WR1 , outputs of the encoder ,are error ,In fig 2,CLKis the signal clock ;CLK2 is output of the divider and CK1 is the output of the NAND gate.
