CMOS数字电路的容错结构研究+文献综述

摘要现如今，数字电路和系统的器件尺寸的减小、功耗降低和运行速度增加，大大降低了数字电路的噪声容限，使得CMOS电路的可靠性受到威胁。因此，对于数字电路和系统的容错性能要求也越来越高。本文首先研究了2014年6月Journal Electron Testing发布的A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems这篇文章中提出的一种新的混合容错结构，然后在此基础上运用动态可重构技术构建另一个数字容错结构，并且将混合容错结构和动态可重构结构两者的参数进行对比。本文也对传统容错技术进行了简介，同时运用传统容错技术中的三模冗余技术构建了一个数字容错系统，作为上述比较的参照。最后，本文选取了ISCAS85 benchmark电路中三个大型的电路，来测试三个系统的容错性能，并比较了在可靠性提高的同时，不同的容错结构在面积、功耗参数上的变化。30515
关键字: 容错,混合容错，动态可重构，三模冗余
毕业设计说明书(毕业论文)外文摘要
Title   The research on fault tolerant architecture of CMOS digital circuits
Abstract
Nowadays, with the size of devices of digital systems and circuits becoming smaller, the power of devices lower and the speed of devices faster, the noise tolerance of digital circuits decreases, which threatens the robustness of CMOS circuits. Thus, the requirement of fault tolerance of these circuits is higher. This paper, at first, studied one research paper called A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems that published in June 2014, and then we built another fault-tolerant architecture by employing dynamically reconfigurable technique based on the original architecture. In the next, we compared these two fault-tolerant architectures in some aspects. This paper also introduced the traditional fault-tolerant technique, and presented one architecture based on triple module redundancy which served as the standard of the comparison stated above. Finally, this paper selected three large circuits of ISCAS85 benchmark circuits in order to testing the fault tolerant ability of the architecture above. And we presented the result of comparison between traditional TMR, hybrid fault-tolerant architecture and the architectures employing dynamically reconfigurable technique using ISCAS'85 benchmark circuits.
Keywords: Fault tolerance, dynamically reconfigurable technique，
           hybrid fault-tolerant architecture, TMR本科毕业设计说明书          第 I 页
目    次
1.    绪论.1
1.1 混合容错结构和动态可重构技术1
1.2 课题的意义2
1.3 课题的主要工作2
1.4 论文的章节安排3
2. 容错技术的结合---混合容错技术.4
2.1 容错技术简介4
2.2 混合容错结构6
2.3 混合容错结构在ISE中的实现与仿真测试.12
2.4 本章小结.23
3．动态可重构技术及其应用24
3.1 局部动态可重构技术简介.24
3.2 实现动态可重构技术的软硬件平台.27
3.3 局部动态可重构的具体软件实现过程.31
3.4 本章小结.56
4．混合容错技术与动态可重构技术的比较结果.57
4.1 ISCAS’85电路57
4.2 混合容错结构的面积和功耗.59
4.3 动态可重构结构的面积和功耗.63
4.4 混合容错结构和动态可重构结构参数比较结果.67
4.5 本章小结.70
结论.71
致谢.72
参考文献.73
本科毕业设计说明书        第 1 页 CMOS数字电路的容错结构研究+文献综述:http://www.751com.cn/tongxin/lunwen_26247.html