The basic elements of printed code are  bars and half-bars representing binary “l”’s and “0”’s  respectively. These bars are printed in one of two for  matting ?elds, namely, A-?eld or B-?eld. A-?eld identi  ?es 5 digit ZIP code containing 32 bars and 9 digit ZIP  code with 52 bars. B-?eld expands the 5 digit At-?eld to  include 37 additional bars to comprise a 9-digit ZIP  code.  With further reference to FIG. 3, the operator selects  the Mode Select 32 switch to run “Operator Paced”  mode. The Main Processor and Memory 42 which is  constantly looking at the Mode Select 32 inputs,  through the I/O Data Bus Controller 41 now knows  which program to run in memory. Also the Mode Se»  lect 32 switch sets the Data Path Controller 44 to obtain  Keyboard I/O Interface 43 data and sends it to EZR  28d by way of twenty signal lines. The Main Processor  and Memory 42 now waits for signals from the Key  board 20 as the operator keys in the ZIP code informa  tion. These signals pass through the Data Path Control  ler 44, Keyboard I/O Interface 43 and are latched into  the I/O Data Bus Controller 41, where they are read by  the Main Processor 42. The Main Processor and Mem  ory 42 assembles the information and determines the  equivalent POSTNET bar code. A “clutch” signal is  provided to console 12 via line 11 to start the print  cycle. The mail piece 16 in FIG. 1, travelling in the  transport path, is sensed by the Mail Piece Detector 44  (FIG. 4) found in Print Controller/Synchronizer 40.  The POSTNET bar code is printed on the mail piece as  it moves past the Print Head 50 disposed in Code 5  Printer 10. Further downstream, a Bar Code Print De  tector 61 situated in Print Controller/Synchronizer 40,  checks the print quality to see if proper printing took  place. The Main Processor and Memory 42 also trans  mits the keyed information to the EZR 28d through the  data path comprising I/O Data Bus Controller 41, Key  board I/O Interface 43 and Data Path Controller 44.  This information enables EZR to sort the mail piece to  the proper bin. If the Console Code Printer 10 is not  being used and the Mode Select 32 is set to “Manual"  (no print), the Data Path Controller 44 allows the key  board signals to be transmitted directly to EZR I/O  Station 28d as in the present manner.  With reference to FIG. 4, the following provides  more detailed information on the Data Path Controller  44, Keyboard I/O Interface 43, U0 Data Bus Control  ler 41, Main Processor and Memory 42 and Print Con  troller/Synchronizer 40.  The Data Path Controller 44 is used to interconnect  the Console Code Printer interface 30 with Keyboard  20 and EZR 28. Reed relays 68 are provided to physi  cally switch between EZR 28 and Keyboard 20 or EZR  28 and Console Code Printer Interface 30. The Key  board I/O Interface 43 includes all of the interconnec  tions required to convert keystrokes from Data Path  Controller 44 to binary coded decimal (BCD) unit 66  and to provide debounce to ?lter out noise from the  keyboard and N-key rollover protection for simulta  neous keying in unit 77. It also converts BCD to Deci  mal in unit 67 and interfaces to the I/O Data Bus Con  troller 41 5-bit bidirectional port.  The U0 Data Bus Controller 41 is a programmable  interface designed for use with microcomputer systems.  Its function is that of a general purpose I/O unit to  interface peripheral equipment to the microprocessor  system bus. The U0 Data Bus Controller 41 performs  three operations: Basic I/O, Strobed Output and Bidi  rectional Bus. Basic I/O provides simple input and out  put operations, for example, 3-bit inputs from Mode  Select 32 or 2-bit outputs to Counter 59. Strobed Output  is a “handshaking” device used to interface with the  Shift Register 52. Four signals namely, OBF, ACK,  INT and Clo_ck Pulse (1)1 and AND gates 75 and 76 are  utilized. When signals INT and OBF go low, INT al  lows data to be loaded into the Shift Register 52 upon  the next clock pulse ¢1; also ¢1 allows the ACK signal  to go low and informs the I/O Data Bus Controller 41  that data has to be accepted. The OBF goes high due to  the ACK going low. ACK goes high on the next clock  pulse (b1 and in turn pulls INT high. Clock pulse ¢1  then allows data to be shifted out of the Shift Register  52. The third operation, Bidirectional Bus, allows both  transmitting and receiving data on a single line such as  the interface to Keyboard I/O Interface 43 or 8-bit Data  Bus to Main Processor and Memory 42.  The Main Processor and Memory 42 are comprised  of three basic blocks, CPU 70, PROM 73 and RAM 72.  Communication between blocks and I/O Data Bus  Controller 41 is accomplished by an 8-bit Data Bus,  8-bit Address Bus and R/W pulse. The CPU 70, via  programs stored in PROM 73, controls synchronization  of data from keyboard 20 via Interrupt Signal INTI to  the CPU 70 and sends more POSTNET data to Shift  Register 52 via Interrupt Signal, INT2. Upon actuation  of the advance key from keyboard 20, the “clutch”  signal line 11 is sent by the CPU 70 to console 12, syn  chronizing output data to EZR 28. 分拣机的打印机系统英文文献和中文翻译(3):http://www.751com.cn/fanyi/lunwen_34316.html