图14 小时低位计数模块元件图
小时低位计数子程序：
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY hl IS
PORT   (clk_1s : IN STD_LOGIC;
iset : IN STD_LOGIC;
flag : IN STD_LOGIC;
iset_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addr_1s : OUT STD_LOGIC_vector(3 downto 0);
os : OUT STD_LOGIC);
END hl;
ARCHITECTURE hl_architecture OF hl IS
BEGIN
k1:process(clk_1s,iset)
variable count:integer range 0 to 10:=0;
begin
if iset='0' then
count:=CONV_INTEGER(iset_addr);
addr_1s<=iset_addr;
elsif rising_edge(clk_1s) then
if flag='1' then
if count=3 then
os<='1';
count:=0;
addr_1s<=CONV_STD_LOGIC_VECTOR(count,4);
else
os<='0';
count:=count+1;
addr_1s<=CONV_STD_LOGIC_VECTOR(count,4);
end if; else
if count=9 then  os<='1';
count:=0;
addr_1s<=CONV_STD_LOGIC_VECTOR(count,4);
else  os<='0';
count:=count+1;
addr_1s<=CONV_STD_LOGIC_VECTOR(count,4);
end if;
end if;
end if;
end process k1;END hl_architecture;
(4) 小时高位计数模块
小时高位模块主要完成小时高位1和2之间的变换，同时当小时高位为2是，将是flag赋值为高电平，当为1是，flag变为低电平。iset为低电平时，小时高位由外部控制按键输入，当iset为高电平时开始计数，该模块框图如图15所示。
 
  图15 小时高位计数模块元件
小时高位计数子程序：
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY hh IS
PORT  (clk_1s : IN STD_LOGIC;
iset : IN STD_LOGIC;
iset_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addr_1s : OUT STD_LOGIC_vector(3 downto 0);
flag: OUT STD_LOGIC);
END hh;
ARCHITECTURE hh_architecture OF hh IS
BEGIN
k1:process(clk_1s,iset)
variable count:integer range 0 to 2:=0;
begin
if iset='0' then
count:=CONV_INTEGER(iset_addr);
addr_1s<=iset_addr;
if count=2 then
flag<='1';
else flag<='0';
end if;
elsif rising_edge(clk_1s) then
     if count=2 then
flag<='0';  count:=0;
addr_1s<=CONV_STD_LOGIC_VECTOR(count,4);
elsif count=1 then
flag<='1';
count:=count+1;
addr_1s<=CONV_STD_LOGIC_VECTOR(count,4);
else
flag<='0';
count:=count+1;
addr_1s<=CONV_STD_LOGIC_VECTOR(count,4);
end if;  end if;
end process k1;
END  
小时高位计数仿真波形如图16所示。   
图16 小时高位计数模块仿真波形
4.3 译码显示模块
该模块完成对计数器编码信息的译码工作，驱动数码管显示相应的数字。时钟扫描信号为分频器输出的另一500Hz高频脉冲信号，addr[30]为输入时间信号，经过译码转换后输出到LED中显示[11]。该模块的输入端口clk是频率为500Hz的扫描时钟，故每一位显示的时间为2ms，需要扫描4个数码管，故显示间隔为8ms。译码模块逻辑图如图17所示：
 
图17 译码显示模块元件
译码显示模块子程序：
LIBRARY  IEEE;
    USE IEEE.std_logic_1164.ALL;
  ENTITY drive IS
PORT  ( clk:in std_logic;addr : IN STD_LOGIC_vector(3 downto 0);
led : OUT STD_LOGIC_vector(7 downto 0) );
END drive;
ARCHITECTURE behave OF drive IS
SIGNAL sel : STD_LOGIC_vector(3 downto 0);
BEGIN VHDL基于FPGA的数字时钟设计+电路图(6):http://www.751com.cn/zidonghua/lunwen_1332.html