摘要在爆炸场中，爆炸后产生的地震波会对地面和建筑物产生冲击和震动，使其在空间产生三维加速度。测量地震波对地面和建筑物冲击震动而产生的三维加速度，对建筑物的抗震能力分析、爆炸威力的评价等具有重要意义。由于常用的硬线测试技术中，存在信号线易断、易抖动、难安装等问题。因此，本文提出了针对爆炸场地震波对地面和建筑物冲击震动产生三维加速度的测量方法。 61186
通过对地震波的分析，提出了存储测试装置的系统性能指标；对各种加速度传感器的对比，选择了ICP加速度传感器；根据所选传感器的电气特性，设计了相应的信号调理电路；基于FPGA技术，设计了将模拟信号转换为数字信号的AD转换电路、存储器电路和RS232串口通信电路；根据各电路对电源的不同需求，设计了可行的电源电路；在QuartusII9.0软件环境下，使用VerilogHDL硬件描述语言对硬件电路进行了各功能模块的编写，并通过LabVIEW8.6编写了上位机通讯软件，实现了对三通道加速度信号的触发设置、数据读取等功能；对加速度信号调理电路、电源电路和基于FPGA的数字电路分别调试，验证了实验方案的可行性。模拟实验结果表明，所设计的存储测试装置是可行的，具有实际工程参考价值。
毕业论文关键词 三维加速度，存储测试，FPGA
毕业设计说明书（论文）外文摘要
Title Stored testing and measuring of three-axis acceleration
Abstract In the field of explosion, the seismic wave produced after the explosion will impact the ground and buildings, which is the cause of 3D-acceleration in space.It is significant to measure the 3D-acceleration on the analysis of seismic capacity and brisance. Because the signal wire is easy to break and shake, and hard to install in the commonly used hard-wire methods. In this situation, the stored testing has been carried out.
Through the analysis of the effece to the target structure caused by the seismic wave, the system performance index of the stored testing device has been proposed; Through the comparison of various acceleration sensor, the ICP acceleration sensor has been chosen; According to the electrical characteristics of the selected sensor, a signal processing circuit has been designed; Based on the FPGA technology, by AD conversion circuit which is used to convert the analog signal to the digital signal memory circuit and RS232 serial communication circuit has been designed; According to the different needs of the power supply circuit, the power circuit has been reasonably designed; In the environment of QuartusII 9.0 software, we use Verilog HDL for the description of various modules of the hardware circuit, And we has developed a software interface for the host computer using LabVIEW 8.6 software, accomplished the setup of internal trigger and data read function of the 3 acceleration signals; Through debuging the signal processing circuit, power circuit and digital circuit based on FPGA, we verified the feasibility of the scheme.The results show that, storage test device is feasible, and has reference value for engineering application.
Keywords three-axis acceleration, stored testing, FPGA
1 绪 论 3
1.1 课题研究背景及意义 3
1.3 本论文主要研究内容 6
2 总体方案 7
2.1 系统性能指标 7
2.2 总体方案设计 FPGA三维加速度存储测试装置研制:http://www.751com.cn/zidonghua/lunwen_66838.html