[11] Murphy, D., Gu, Q.J., Yi-Cheng Wu, et al. A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver[J]. IEEE Journal of Solid-State Circuits,2011, 46(7):1606-1617.
[12] Maheshwari, S.K., Fang, E., Aggarwal, S.. 32-nm SOI programmable, high-bandwidth 8.0-GHz digital PLL[C]. Custom Integrated Circuits Conference (CICC), 2011:1-4.
[13] 舒海涌. PLL频率综合器中整数和小数分频器设计与实现[D]. 东南大学,2010.
[14] 蒋立平. 数字逻辑电路与系统设计[M]. 北京:电子工业出版社,2008.
[15] Boon, C.C., Krishna, M.V., Do, M.A., et al. A 1.2 V 2.4 GHz low spur CMOS PLL synthesizer with a gain boosted charge pump for a batteryless transceiver[C]. Radio-Frequency Integration Technology (RFIT), 2012:222-224.
[16] 孙振华. WSN PLL频率综合器中分频器的设计[D]. 东南大学,2012.
[17] 康建颖. 频率综合器中的分频器电路设计[D]. 东南大学,2009.
[18] 杨伟伟. 极低电压极低功耗的射频VCO及其预分频器设计研究与实现[D]. 浙江大学,2012.
[19] 陆磊. 无线传感网频率综合器前置分频器的设计与实现[D]. 东南大学,2009.
[20] Yuan, J., Svensson, C.. High-speed CMOS Circuit Technique[J]. IEEE Journal of Solid-State Circuits, 1989, 24(1):62-70.
[21] Xiao Peng Yu, Do, A.V., Wei Meng Lim, et al. Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler[J]. IEEE Transactions on Microwave Theory and Technique, 2006, 54(11):3828-3835.
[22] Craninckx, J., Steyaert, M. S J. A 1.75-GHz/3-V dual-modulus pide-by-128/129 prescaler in 0.7-μm CMOS[J]. IEEE Journal of Solid-State Circuits, 1996, 31(7):890-897.
[23] 朱凯. 应用于GPS接收机频率综合器分频器设计[D]. 上海交通大学,2009.
[24] 马雪坡. 高速分频器研究[D]. 天津大学,2009.
[25] Zhiqun Li, Qinqing Cao, Xiaodong Qi, et al. Design of a low power 5-GHz frequency synthesizer for WSN applications[C]. IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2012:228-230.
[26] Singh, U., Green, M.. Dynamics of high-frequency CMOS piders[C]. IEEE International Symposium on Circuits and Systems, 2002:421-424.
[27] 毕查德·拉扎维(Behzad Razavi). 模拟CMOS集成电路设计[M]. 西安:西安交通大学出版社,2003.
[28] 陆学斌,董长春,韩天. 集成电路版图设计[M]. 北京:北京大学出版社,2012.
[29] 曾庆贵,姜玉稀. 集成电路版图设计教程[M]. 上海:上海科学技术出版社,2012.