摘要常用的测量频率的方法有很多，比如说直接测频法（M法）、周期测量法（T法）、等精度法（M/T法）、全同步频测法等。此次设计的全同步频测法相对于前三个的优势在于它的精确度比较高。其测频原理为在某一信号T秒时间里重复变化了N次，则根据频率的定义可知该信号的频率为N/T。41204
本论文对频率测量的方法进行了阐述，比较了它们之间的优缺点，对全同步测频提出了自己的设计方法,由于门电路具有延时效应，当时钟信号与被测信号达到同步的时候开始计数，通过相位同步来消除误差，计数后通过一系列步骤来得出频率。再次达到同步的时候停止计算。
根据全同步频率计的设计方法，采用Verilog语言进行模块设计和编译。利用EDA的自上而下的设计流程，在QuartusII上对每个模块进行仿真和调试，最后对整体系统进行仿真来验证设计的成功。
该论文有图11幅，参考文献20篇。
毕业论文关键字：频率计  Verilog语言  全同步  仿真
Design for all synchronous digital frequency meter based on FPGA
Abstract
The commonly used method of measuring frequency has a lot of, such as direct frequency measurement method (M),cycle measurement method (T), precision method (M/T),all synchronous frequency measurement method, etc.The design of the identical frequency measurement method for the first three's advantage is its precision is higher.Its frequency measuring principle is a signal changed in T seconds time repeat N times,Then according to the definition of the signal frequency frequency is N/T.
This thesis expounds the method of frequency measurement,Compares the advantages and disadvantages between them,I proposed my own design for full with pacing frequency.Because of the gate has delayed effect,At the time the clock signal and the measured signal synchronous start counting,through the phase synchronization to eliminate the error,through a series of steps to frequency after counting.At last,stop counting again to achieve synchronization.
According to the design method of synchronous frequency meter, this thesis using Verilog language module design and compilation.Make use of EDA top-down design process, simulation and debugging of each module in QuartusII.Finally, the whole system simulation to verify the success of the design.
There are 11 pictures and 20 references in this design.
Key words：Frequency meter  verilog HDL   All synchronous   simulation
目 录
摘要.I
Abstract.Ⅱ
目录 Ⅲ
图清单Ⅴ
变量注释表Ⅴ
1 绪论1
1.1课题研究背景.1
1.2频率计概述.1
1.3频率计发展现状.2
1.4频率计设计原理和方法.2
1.5QuartusII的软件介绍.3
2 基于FPGA的系统设计.4
2.1EDA技术.4
2.2FPGA简介.4
2.3查找表的原理和结构.5
2.4基于FPGA的设计方法5
2.5Verilog HDL语言6
3 全同步测量频率方法7
3.1常用的测量频率的方法.7
3.2全同步数字频率计的设计方法.10
4 FPGA功能模块设计13
4.1计数器模块.13
4.2锁存器模块.14
4.3选择电路.15
4.4控制电路.16
4.5显示电路.17
4.6频率计整体电路.18
5 下载验证20
5.1系统配置.20
6 结论22
参考文献23
致谢24
图清单
图序号    图名称    页码
图2-1    查找表结构图    5
图3-1    多周期同步测频原理图    8
图3-2    多周期同步频测的波形图    9
图3-3    系统原理图    10
图3-4    内部模块设计    12
图4-1    计数器原理图    13 基于FPGA的全同步数字频率计设计+仿真图:http://www.751com.cn/zidonghua/lunwen_41190.html