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摘要随着科学技术的不断发展，科学技术已经渗透到各种各样的领域中，生活、学习、娱乐等领域对科学技术的依赖，促进了科学技术的发展。抢答器的设计方法多种多样，有基于的单片机的抢答器，基于PLC的抢答器，基于FPGA的抢答器等等。选择一个既经济又多功能化、且设计制作便捷的方法成为当今抢答器设计的主题。39758
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随着EDA技术的发展，可编程逻辑器件的内部I/O端口资源丰富，且可编程逻辑器件的灵活性很强，可以设计多路抢答器。采用FPGA作为芯片，硬件电路简单明了，便于系统文护，且文护费用低，FPGA系统采用模块化的思想，整个系统由若干个模块组成，简单明了的思想更加便于新手学习应用。
由于FPGA设计模块化的特性，本次做的八路抢答器具有五个模块：倒计时模块、抢答模块、加减分模块、蜂鸣器模块以及数字显示模块。八路抢答器具有八组选手抢答功能、10秒倒计时功能、加减分功能以及数码显示组号分数的功能。本次设计的程序采用Verilog语言编程，采用模块化的思想，自上而下，对每个模块进行编程，利用Quartus ii软件进行编译仿真，实现八路抢答器的功能。
毕业论文关键词：FPGA 八路抢答器 Verilog HDL Quartus II
Abstract With the development of science and technology,science and technology has penetrated into a wide variety of areas,Dependent on life, learning, entertainment and other fields of science and technology, and promote the development of science and technology.The designs of responder are varies, There are microcontroller-based Responder, Responder plc based FPGA-based Responder and so on.Selecting an economical and multi-functional, and easy way has been today's responder designed themes.
With the development of EDA technology,the programmable logic device has rich I / O port resource inside,and the programmable logic device has a strong flexibility, it can be used to design the multiple responder.Using FPGA as a chip,the hardware circuit is simple,and the costs on maintenance is low .FPGA systems use modular thinking,The system consists of several modules, simple ideas make it easier for novices to learn the application.
Since FPGA design modularity, the design we do has five modules :Countdown module, Group module, add and subtract points module, buzzer module and a digital display module.Responder features eight groups of players, 10 seconds countdown function, addition and
subtraction as well as sub-function digital display group number score function.The program design using Verilog language programming,Using the modular thinking,Programming of each module,Use Quartus ii compile to simulation and software,Achieving eight Responder function.
Keyword: FPGA Eight Responder Verilog HDL Quartus II
目录
摘 要 I
Abstract II
1 绪论 1
1.1 课题研究背景及意义 1
1.2 国内外研究现状 1
1.3 本设计的内容及要求 2
2 相关知识介绍 4
2.1 FPGA的简介 4
2.1.1 FPGA的发展与趋势 4
2.1.2 FPGA的工作原理及基本特点 4
2.1.3 FPGA的开发流程 5
2.1.4 FPGA的配置 6
2.2 Verilog HDL的介绍 7
2.3 Quartus Ⅱ软件的介绍 7
3 抢答器的整体设计 9
3.1 FPGA控制器设计 9
3.2抢答器功能及模块划分 10
3.3抢答器各模块设计 11
3.3.1 抢答器设计 11