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摘要本论文实现了以CPLD芯片为时序逻辑控制器件的，雷达回波信号的数据采集系统。该系统能够对两种雷达回波信号进行数据采集，一种是步进频率雷达回波信号，一种是线性调频连续波回波信号。通过开关来转换来控制对这两种数据信号的采集。对于步进频率雷达回波信号，在一个完整的频率周期内有64个步进频率回波信号，对每个回波信号以60MHz的速率进行256点采样，采满16K点为止。对于连续波雷达信号采样，则连续采满16K点为止。63591
本论文的数据采样系统由以下部分组成：A/D转换，FIFO同步存储器，DSP核心处理芯片，CPLD时序及逻辑控制电路，FLASH数据存储器，SDRAM动态存储元件，UART通信串口。其中FLASH,SDRAM,UART为DSP芯片外部扩展的存储器和接口，由CPLD内部通过逻辑控制，产生每个外扩芯片的片选信号，复位信号，输出使能信号及控制信号。对于FLASH芯片，则在CPLD内部产生FLASH翻页用的各种寄存器和页选择引脚。对于UART串口的通信串并转换芯片，则在CPLD内部产生通道选择寄存器，数据发送和接收的使能寄存器。
首先利用CPLD器件产生A/D转换的触发信号和采样时钟信号。根据雷达系统的同步信号，产生A/D采样的触发信号，对回波开始采样。本设计需要对两种回波信号采集，所以需要CPLD通过逻辑控制产生两种A/D采样时钟。一种采样时钟是在A/D触发信号的下降沿来到时，输出256个60MHz的脉冲循环64次。另一种采样时钟是当A/D触发信号来到后输出连续的60MHz的脉冲，直到FIFO写满为止。在A/D芯片采样时钟开始工作的7个周期后，数据才会从A/D芯片输出。此时需要通过FIFO的WCLK时钟，将数据写入FIFO中去，FIFO的WCLK也需要通过CPLD逻辑控制。当FIFO满后，DSP采用中断的方式从FIFO中开始读数据，然后进行数据处理，最后数据通过通信串口UART输出。
本论文中关于CPLD的逻辑时序控制功能，由QUARTUSⅡ软件设计完成。最后通过JTAG接口，将QUARTUSⅡ中的程序下载到硬件上，通过实际运行验证了逻辑设计的合理性和正确性。
毕业论文关键词：CPLD DSP QUARTUS Ⅱ 数据采集系统 采样时钟
毕业设计说明书（论文）外文摘要
Title The high-speed data collecting system based on CPLD
Abstract
The paper designs a system to collect radar echo signal based on the timing control device CPLD. It can gather two kinds of radar echo signal including stepping frequency radar echo signals and continuous echo signals. We have a switch to collect these different kinds of signals. For stepping frequency radar echo, we have 64 stepping frequencies in a complete cycle of frequency. Gathering 256 analog data for every echo frequency with the rate of 60MHz, we can get 16384 analog data on total. For continuous echo, we continuously gather 16384 analog data with the 60MHz sampling rate. Then these analog data were converted into digital data which can be processed by DSP.
The sampling system in this paper contains several parts which are A/D conversion, FIFO asynchronous memory, DSP core processing chip, CPLD timing and logic control circuit, FLASH data storage devices, SDRAM dynamic data storage devices, and UART communication port. FLASH, SDRAM, and UART chips are the external expansion memory and interface of DSP chip controlled by CPLD port. Through internal logic and timing development, CPLD generates chip-select signal, the reset signal, and output enable signal for each device. As for the FLASH chip, CPLD generates registers for the page-selecting of FLASH chip and page-selecting pins. When it comes to UART serial communication chip, the registers for channel-selecting, and sending and receiving data pins are produced in CPLD.
At first, the A/D conversion trigger signals is obtained by the program in CPLD chip. Then these trigger signals enable A/D sampling clock to gather analog data of radar echo signals. Because there are two kinds of echo signals, so it is necessary for CPLD to give two kinds of A/D sampling clock. One kind of clock is 256 impulses with the rate of 60MHz after each sampling trigger signal, the other is continuously 60MHz impulses till the FIFO chip full. Then DSP chip gives a signal to stop the sampling impulses. After the A/D conversion device starts working seven cycles, digital data will appears on the output data lines. At this moment, FIFO writing clock is needed to send digital data into FIFO memory. Then writing clock is also designed in the CPLD. When FIFO memory is full, DSP will read these data to operating. At last, the final data will output through UART serial communication port.